A logic option that causes a register (flipflop) to power up with a high logic level(1). If this option is turned off for a register, it causes the register to power up with a low logic level (0). If this option is turned on for an input pin, it is automatically transferred to the register that is driven by the pin if the following conditions are present:

• There is no intervening logic, other than inversion, between the pin and the register.

• The input pin drives the data input of the register.

• The input pin does not fan-out to any other logic.

If this option is turned on for an output or bidirectional pin, it is automatically transferred to the register that feeds the pin if:

• There is no intervening logic, other than inversion, between the register and the pin.

• The register does not fan-out to any other logic.

This option is ignored if it is assigned to anything other than a register, or to a pin with any logic configuration other than those described above. This option is available for all Altera^® devices supported by the Quartus^® II software.

Back to Top