A parameter is an attribute of a megafunction, macrofunction, or certain primitives that determines the logic created or used to implement the function, that is, a characteristic that determines the size, behavior, or silicon implementation of a function. The parameter information can be used to determine the actual primitives and other subdesigns needed to implement the logic of the function.

A parameterized function or module is a function whose behavior is controlled by one or more parameters. Some logic functions, such as the functions in the library of parameterized modules (LPM), are inherently parameterized and require parameter values to be assigned. When you use an existing parameterized function, such as an LPM function, you can customize the parameters used and assign parameter values on an instance-by-instance basis. In a Block Design File (.bdf), you can customize an instance (that is, a symbol) with the Parameters tab of the Block Properties dialog box (Edit menu). In an Text Design File (.tdf), you can declare parameters and assign values when you create an instance with an Instance Declaration or an in-line logic function reference. In a VHDL Design File, you can assign parameter values to an instance of a logic function in the Generic Map of its Component Instantiation Statement. In non-VHDL files, parameter values can be inherited from top-level entities in a project. The Compiler searches for parameter values in the parameter value search order.

Parameters can be assigned to any individual instance of a megafunction in the Quartus^® II software to control its size or implementation. The Quartus II software also allows you to assign global, project-wide default values for parameters.

When you create a parameterized design file, you can specify the parameters used within that file and optional default parameter values (which are used only if no parameter values are specified elsewhere). In a BDF, you specify the parameters used within the current file with PARAM primitives; in a TDF, the parameters used within the current file are specified in a Parameters Statement; in a VHDL Design File, parameters are specified in the Generic Clause of the Entity Declaration.

A parameter name can contain up to 32 name characters. Once you create a parameterized design file, you can use the Create/Update > Create AHDL Include Files for Current File command (File menu) and the Create/Update > Create Symbol Files for Current File command (File menu) to create default AHDL Function Prototypes (in AHDL Include Files (.inc)) and symbols (in Block Symbol Files (.bsf)), respectively, that include the names (but not the values) of parameters used within the file. You can edit the parameters and parameter values for a BSF with the Parameters tab of the Symbol Properties dialog box (Edit menu). These parameter names and values then appear as the defaults for each instance of the symbol when it is first entered in a BDF. Once you enter the symbol in a BDF, these default parameters and values can be customized with Parameters tab of the Block Properties dialog box (Edit menu) on an instance-by-instance basis.

The Quartus II software allows you to assign global, project-wide default values for parameters with the Parameter Properties command (Edit Menu).

The following general guidelines apply to parameters:

All logic options can be assigned as parameters for individual instances of mega- or macrofunctions. A logic option that is assigned to a logic function instance as a parameter overrides the global project default synthesis style--which is specified with Assignment Organizer dialog box (Assignment menu)--for that instance. However, if an instance has the same logic option assigned both as a parameter and as an individual logic option, the logic option setting overrides the parameter setting.

You cannot assign a value to the predefined Altera^® parameter DEVICE_FAMILY, which represents the device family assigned for the project. However, you can use the parameter value in comparisons.

The predefined Altera LPM_PIPELINE and LATENCY parameters can be assigned to an instance of a mega- or macrofunction. However, the parameter applies only to that instance, and is not inherited by the subdesigns of that instance.

All logic options can be assigned as parameters for individual mega- or macrofunctions. However, logic options cannot be assigned global, project-wide default parameter values.

Parameters appear on the top right corner of a symbol in the Block Editor or Symbol Editor if you activate Show Parameter Assignments (View menu).

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