The name given to a signal in a design file. A node name can contain an unlimited amount of the following name characters: A to Z, a to z, 0 to 9, slash (/), dash (-), and underscore (_). Hierarchical node names can contain an unlimited amount of characters, including vertical bar (|), colon (:), and period (.). Case is not significant, except in Verilog HDL. In Verilog HDL, nodes are called "nets."

Some restrictions apply to names in VHDL Design Files (.vhd), Verilog Design Files (.v), and unquoted port and symbolic names in AHDL Text Design Files (.tdf).