The Compiler module that synthesizes and performs technology mapping on the logic in the design entity or project's files.

The Logic Synthesizer uses several algorithms to minimize gate count, remove redundant logic, and utilize the device architecture as efficiently as possible. Processing can be customized with logic option assignments. This module also applies logic synthesis techniques to help implement timing requirements for a project.

For projects that use JK or SR flipflops, the Logic Synthesizer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly.

The Logic Synthesizer also synthesizes equations for flipflops to implement state registers of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the state machine. These encodings are chosen to minimize the resources used.

The Logic Synthesizer then uses an algorithm-based expert system to group the project requirements for I/O pins, tri-state buffers, and register and combinatorial resources into individual logic cell-sized units. In addition, in device architectures with shareable expander product terms, the numbers of logic cells and expander product terms are balanced to use resources efficiently. As part of the logic minimization and optimization process, logic and nodes in the project may be changed or removed.

The Messages window and the Messages section of the Report window or Report File display any messages the Logic Synthesizer generates. The Status window and the Processing Time section of the Report window or Report File record the time spent processing in the Logic Synthesizer during project compilation.

Back to Top