A primitive, megafunction, macrofunction, or state machine, which may be represented as either a name or a symbol in a design file.

A logic function can be a top-level logic function, which is a logic function that is not below any other logic function in a project hierarchy, or a lower-level logic function (or, "subdesign"). A top-level logic function can contain any number of lower-level logic functions, and is the "parent entity" for the lower-level logic functions. You can set a top-level logic function as a simulation or compilation focus.

You can set a lower-level logic function as the compilation focus; however, when you do so, the Compiler uses the parameters and assignments from the top-level, parent entity of that lower-level logic function during compilation.

When you try to set a lower-level logic function as the simulation focus, the Quartus^® II software automatically creates a top-level logic function for that lower-level logic function, and sets the new top-level logic function as the simulation focus.

The following logic function types are supported in the Quartus II software:

• AHDL subdesigns
• Block Design File (.bdf) entities
• EDIF cells inside EDIF designs
• Verilog HDL modules
• VHDL entity-architecture design units

Logic functions are also referred to as design entities or entities.

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