A generic term that refers to an assignable physical resource in the interior of an Altera® device.
You can assign a node or entity to one of the following locations:
| APEX™ 20K, APEX™ II, ARM®-based Excalibur™ |
FLEX® 6000 | Mercury™ | ACEX® 1K FLEX 10KE |
MAX® 3000, MAX 7000 | Cyclone™ | Stratix™ Stratix™ GX |
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An individual logic cell |
An individual logic cell |
An individual logic cell |
An individual logic cell |
An individual I/O pin |
An individual logic cell |
An individual logic cell |
| An individual I/O pin | An individual I/O pin | An individual I/O pin | An individual I/O pin | A macrocell | A LAB | An individual I/O pin |
| A Logic Array Block (LAB), Embedded System Block (ESB), row, or column |
A LAB, row, or column | A LAB, ESB, or row | A LAB or Embedded Array Block (EAB) | A LAB | A M4K memory block | A LAB |
| An individual MegaLAB™ row | An ESB row | An individual row | A PLL | An M-RAM or an M512 or M4K memory block | ||
| An individual MegaLAB column | A ClockLock® PLL | An individual column | A Custom Region | A DSP block | ||
| Half an individual MegaLAB row | A Custom Region | A Custom Region | A PLL | |||
| Half an individual MegaLAB column | A SERDES receiver | |||||
| An individual section | A SERDES transmitter | |||||
| An individual Fast Region | A Custom Region | |||||
| A Custom Region |
You can make assignments to locations using the Assignment Organizer dialog box (Assignment menu) and the Floorplan Editor. You can also make assignments to regions or custom regions, which are multicell locations, in the Floorplan Editor Regions window. When you assign a logic function to a general location such as a LAB, EAB, ESB, row, or column, the Compiler can choose the best logic cell or embedded cell within the LAB, EAB, ESB, row, or column to use to implement the logic.
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