JTAG boundary-scan testing

Testing that isolates a device's internal circuitry from its I/O circuitry. This testing is made possible by the Joint Test Action Group (JTAG) Boundary-Scan Test (BST) architecture that is available in all Altera^® devices supported by the Quartus^® II software except EPC1, EPC1441, and FLEX^® 6000 devices. Serial data is shifted into boundary-scan cells in the device; observed data is shifted out and externally compared to expected results. Boundary-scan testing offers efficient PC board testing and provides an electronic substitute for the traditional "bed of nails" test fixture.

The full or partial JTAG BST architecture also supports in-system multidevice JTAG chain device configuration.