A logic option that specifies the I/O standard of a pin. Different device families support different I/O standards, and restrictions apply to placing pins with different I/O standards together. For detailed information, refer to the device family data sheet and to Application Note 117 (Using Selectable I/O Standards in Altera^® Devices).

This option is ignored if it is applied to anything other than a pin or a top-level design entity. This option is available for APEX^™ 20K, ARM^®-based Excalibur^™, and Mercury^™ devices only.