Glossary

Inverted Clock timing assignment


Specifies that a register has an inverted clock (the clock path contains a NOT gate). You can assign the Inverted Clock assignment only as a single-point assignment. By default, the Timing Analyzer attempts to automatically detect registers with inverted clocks. However, you can use this assignment in more complex designs to designate inverted clocks the Timing Analyzer cannot auto-detect.

- PLDWorld -

 

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