The use of a logic function in a design file. In the Block Editor, the instance is represented by the instance name in the lower left corner of an object; in the Waveform Editor, the instance is the name of the node. In the Symbol Editor, the instance name is a placeholder for the location of the instance in the Block Editor. In AHDL, instances are declared in one of two forms: an Instance Declaration that declares a variable of the type <primitive>, <megafunction> or <macrofunction>, or an in-line logic function reference. In VHDL, instances of logic functions are declared with a Component Instantiation Statement; registers can also be implemented with Register Inferences. In Verilog HDL, instances are declared with Module Instantiations and Gate Instantiations.

In an AHDL Variable Declaration and a VHDL Component Instantiation Statement, an instance is represented by the instance name followed by a colon and the function name. In a Verilog HDL Module or Gate Instantiation, an instance is represented by the module or gate name followed by the instance name.

In the SignalTap^® II Logic Analyzer, instances are created in the Instance Manager, and each instance name represents an Embedded Logic Analyzer megafunction.

Back to Top