In AHDL, a group is a collection of symbolic names that are treated as a unit. A group name can be specified with a single-range group name, dual-range group name, or sequential group name format.

In VHDL and Verilog HDL, a group is called an array. Examples of VHDL array types are STD_LOGIC_VECTOR and BIT_VECTOR. See "Section 3.2.1: Array Types" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual for more information. Only one- and two- dimensional arrays of scalar elements are supported.

Examples of Verilog HDL array types are memories (which are arrays of register elements or words) and arrays of gate instances and registers. The elements, instances, or registers in the array are specified with a range. See "Section 3.3: Vectors," "Section 3.8: Memories," and "Section 7: Gate and Switch Level Modeling" in the IEEE Std 1364-1995 IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language manual for more information.

In the Waveform Editor and Simulator, a group is a collection of nodes that are treated as a unit. In these applications, a group name can be specified with an arbitrary group name or single-range group name format.

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