A dedicated global input pin-driven or logic-driven signal that passes through the global routing on a device before performing its specified function. The number of dedicated global input pins and/or logic cells needed to use both the true and complement of a global signal varies from device family to device family. Clock, preset, clear, output enable, clock enable, synchronous clear, memory read enable, memory write enable, and synchronous load signals can be global signals; refer to device family data sheets for specific details, which are available from the Literature section of the Altera^® web site.

A global signal can be set during design entry with a GLOBAL primitive. You can use a dedicated global input pin to drive a global signal by feeding its output directly to a GLOBAL primitive. You can also use the output of a logic function as a global signal by feeding its output directly to a GLOBAL primitive. A logic-driven global signal can consume the global routing, which can consume a dedicated global input pin; refer to device family data sheets for specific details. Global signals are available for all devices supported by the Quartus^® II software.

The following global signals are available for each device family:

	ACEX® 1K, FLEX 10KE	APEX™ 20K, APEX™ II, ARM®-based Excalibur™	FLEX® 6000	MAX® 3000, MAX 7000	Mercury™	Cyclone™, Stratix™, Stratix™ GX
Clock Signals
clock
Output Enable Signals
output enable
Register Control Signals
asynchronous clear (clear)
synchronous clear		(LE only)			(LE only)
asynchronous load	(LE only)
synchronous load					(LE only)
asynchronous preset (preset)	(LE only)
clock enable	(I/O) cell register only	(I/O) cell register only
Memory Enable Signals
read enable
write enable

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