functional simulation

A Quartus^® II Simulator mode that uses a pre-synthesis Compiler database to simulate the logical performance of a project (without timing information). You can use Tcl commands, a Vector Waveform File (.vwf), or a text-based Vector File (.vec) to provide vector stimuli. However, the Simulator uses only the sequence of logic level changes in vector stimuli, and not their timing. This type of simulation also allows you to check simulation coverage (the ratio of nodes simulated to the total number of nodes in the design).

Because the database used for functional simulation is generated before logic synthesis, partitioning, or fitting are performed, functional simulation allows you to simulate all nodes in a design entity or project.