The Compiler module, also known as the PowerFit Fitter, that fits the logic of a design into a device. The Fitter selects appropriate interconnection paths, pin assignments, and logic cell assignments.
Using the database updated by the Logic Synthesizer, the Fitter matches the logic requirements of the project with the available resources of a device. It assigns each logic function to the best logic cell location for routing and timing, and selects appropriate interconnection paths and pin assignments.
The Fitter attempts to match any resource assignments made for the design with the resources on the device. If it cannot find a fit, the Fitter terminates compilation. The Fitter can run repeatedly during compilation.
For all Altera® devices supported by the Quartus® II software except FLEX® 6K devices, the Fitter ignores all clique assignments except LAB clique assignments. |
The Processing tab of the Messages window and the Messages section of the Report window or Report File display the messages the Fitter generates. The Status window and the Processing Time section of the Report window or Report File record the time spent processing in the Fitter during project compilation.
- PLDWorld - |
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