A configuration scheme in which an external controller loads design data into one or more APEX^™ II, Stratix^™, or Stratix^™ GX devices via a common data bus. In this scheme, an external controller sends eight bits of parallel data to the APEX II, Stratix, or Stratix GX device per clock cycle. The external controller can be an intelligent host, such as a microcontroller or CPU, or an EPC16 configuration device.