A primitive, megafunction, macrofunction, or state machine, which may be represented as either a name or a symbol in a design file.

An entity can be a top-level entity, which is an entity that is not below any other entity in a project hierarchy, or a lower-level entity (or, "subdesign"). A top-level entity can contain any number of lower-level entities, and is the "parent entity" for the lower-level entities. You can set a top-level entity as a simulation or compilation focus.

You can set a lower-level entity as the compilation focus; however, when you do so, the Compiler uses the parameters and assignments from the top-level, parent entity of that lower-level entity during compilation.

When you try to set a lower-level entity as the simulation focus, the Quartus^® II software automatically creates a top-level entity for that lower-level entity, and sets the new top-level entity as the simulation focus.

The following entity types are supported in the Quartus II software:

• AHDL subdesigns
• Block Design File (.bdf) entities
• EDIF cells inside EDIF designs
• Verilog HDL modules
• VHDL entity-architecture design units

Entities are also referred to as logic functions or design entities.

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