The smallest horizontal interconnect channel in a Stratix^™ or Stratix^™ GX device that connects cells within a Logic Array Block (LAB), DSP block, or M512 or M4K memory block, and in adjacent LABs, DSP blocks, or M512 or M4K memory blocks without using row interconnect resources.

The smallest horizontal interconnect channel in a Cyclone^™ device that connects cells within a LAB or M4K memory block, and in adjacent LABs or M4K memory blocks without using row interconnect resources.