A primitive, megafunction, macrofunction, or state machine, which may be represented by either a name or a symbol in a design file.

A design entity can be a top-level design entity, which is a design entity that is not below any other design entity in a project hierarchy, or a lower-level design entity (or, "subdesign"). A design entity can instantiate any number of lower-level design entities, and is the "parent" for the lower-level design entities.

You can set a top-level design entity as the simulation or compilation focus. You can set a lower-level design entity as the compilation focus; during compilation, the lower-level design entity inherits parameter and assignment settings from the higher-level entities in its hierarchy

When you try to set a lower-level design entity as the simulation focus, the Quartus^® II software automatically creates a top-level design entity for that lower-level design entity, and sets the new top-level design entity as the simulation focus.

The following design entity types are supported in the Quartus II software:

• AHDL subdesigns
• Block Design File (.bdf) entities
• EDIF cells in EDIF designs
• Verilog HDL modules
• VHDL entity-architecture design units

Design entities are also referred to as logic functions or entities.

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