Specifies the default value for the Multicycle Hold requirement (that is, the minimum number of clock cycles required before a register latches a value). The Default Multicycle Hold requirement is overridden on specific nodes by any individual Multicycle Hold requirements. The following table describes the settings for this assignment:

Setting	Description
Same as Multicycle	Specifies that the Default Multicycle Hold requirement should match the value of the Multicycle requirement (that is, that the signal should be latched on the final edge only). This setting is less restrictive than the One setting and generally produces fewer hold time violation warnings.
One	Specifies that the signal should latch on any edge, up to and including the final edge. This setting is more restrictive than the Same as Multicycle setting; however, it is sometimes the default setting used by other timing analysis tools. One is the default setting for this assignment.

Back to Top