The Compiler module that builds a single project database that integrates all the design files in a design entity or project hierarchy.

The Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the fully optimized project. In the beginning, the database contains only the original netlists; at the end, it contains a fully minimized, fitted project, which is used to create one or more files for device programming.

As it creates the database, the Database Builder examines the logical completeness and consistency of the project, and checks for boundary connectivity and syntactical errors (for example, a node without a source or destination). The Database Builder detects most errors, which you can easily correct at this initial stage of project processing.

This module also performs "high-level synthesis." For example, it infers flip-flops, latches and state machines from "behavioral" languages, such as Verilog HDL and VHDL. In addition, it replaces operators, such as + or - with modules from the Altera^® library of implemented parameterized modules (also called "parameterized functions") from LPM version 2.2.0, which offer architecture-independent design entry for Quartus^® II-supported devices.

The Messages window and the Messages section of the Report window or Report File display any messages the Database Builder generates. The Status window and the Processing Time section of the Report window or Report File record the time spent processing in the Database Builder during project compilation.

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