An operator that selects between two expressions within an AHDL or Verilog HDL arithmetic expression. The conditional operator is used in the following format:

<expression 1> ? <expression 2> : <expression 3>

If the first expression is non-zero (true), the second expression is evaluated and given as the result of the ternary expression. Otherwise, the third expression is evaluated and given as the result of the ternary expression.

In AHDL, conditional operators are called "ternary operators."

Back to Top