bus

A thick line in a Block Editor file that represents multiple nodes. A bus carries multiple signals between components of a design, and can represent from 2 to 256 nodes (that is, bits). The signals in a bus can be numbered. For example, the bus A[3..0] represents the signals A3, A2, A1 and A0. All signals in a bus have an inherent order whether or not they are numbered.

In AHDL and Waveform Editor files, a group is synonymous with a bus.

In VHDL, a bus is a guarded signal that may have its drivers, that is signal sources, turned off. In VHDL, a bus is called an array, and is not limited to 256 symbolic names. An example of an array type is STD_LOGIC_VECTOR. See "Section 3.2.1: Array Types" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual for more information. Only one- and two- dimensional arrays of scalar elements are supported.

In Verilog HDL, a bus is an array of nets, and is not limited to 256 symbolic names. See "Section 3.3: Vectors" in the IEEE Std 1364-1995 IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language manual for more information.

You can also enter buses in designs created with other EDA tools. However, you should specify that the buses should be flattened when you generate EDIF netlist files from the designs.

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