assignment

In AHDL and VHDL, assignment refers to the transfer of a value to a symbolic name or group, usually through a Boolean equation. The value on the right side of the equation is assigned to the symbolic name or group on the left.

In Verilog HDL, assignment refers to the transfer of a value to a net or a register, usually through a Boolean equation. The value on the right side of the equation is assigned to the net or register on the left.