A configuration scheme in which the active serial memory interface block loads design data into one or more Cyclone^™ devices. In this scheme, the active serial memory interface block in the Cyclone device controls the configuration process, and configures all of the devices in the chain using the configuration data stored in an EPCS1 or EPCS4 configuration device.

The Quartus^® II Compiler automatically generates SRAM Object Files (.sof) that contain the data for configuring Altera^® devices in an AS configuration scheme.

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