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To perform a timing simulation on your design using the ModelSim® software once you have compiled your design in the Quartus® II software, you can create a script that performs the following steps:
Compiles the <device family>_atoms.v library
Compiles the Verilog Output File (.vo) generated by the Quartus II software during compilation. In this example, the Verilog Output File name is pllsource.vo.
Compiles the test bench file. In this example, the test bench file name is plltest.v.
You can simulate the sample design in the ModelSim software by using the commands shown in the following sample script:
vlib work # Create working directory
vlog /quartus/eda/sim_lib/apex20ke_atoms.v # Read the simulation library
# /quartus/ is the path to Quartus II
vlog pllsource.vo # Compile Quartus II output netlist
vlog plltest.v # Compile test fixture
vsim -t ps work.plltest # Simulate plltest with resolution in ps
add wave /plltest/* # Add the port signals to the waveform view
run 1000 ns # Run the simulation for 1000 ns|
- PLDWorld - |
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