See Also

To specify that the LeonardoSpectrum^™ software should treat the arm_processor.v file, which is created in Example of Creating an Excalibur^™ Embedded Processor Stripe, as a "black box," refer to the following code sample from the top-level design file. In this example, the top-level design file is arm_top.v.

The line //Mentor Graphics® attribute b2v_inst2 NOOPT TRUE instructs the LeonardoSpectrum software to treat the instance b2v_inst2 as a black box.

module arm_top(
	clk_ref,
	masterhclock,
	npor,
	ebiack,
	intextin,
	needed_an_output,
	nreset,
	ebiaddr,
	ebidq
);

input	clk_ref;
input	masterhclock;
input	npor;
input	ebiack;
input	intextin;
output	needed_an_output;
inout	nreset;
output	[24:0] ebiaddr;
inout	[15:0] ebidq;

wire	[31:0] operation;
wire	[31:0] reg_address;
wire	[31:0] reg_wdata;
wire	[31:0] SYNTHESIZED_WIRE_0;
wire	[31:0] SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_20;
wire	[31:0] SYNTHESIZED_WIRE_5;
wire	[2:0] SYNTHESIZED_WIRE_6;
wire	[1:0] SYNTHESIZED_WIRE_7;
wire	[1:0] SYNTHESIZED_WIRE_8;
wire	[31:0] SYNTHESIZED_WIRE_9;
wire	[31:0] SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;
wire	SYNTHESIZED_WIRE_12;
wire	[31:0] SYNTHESIZED_WIRE_13;
wire	[1:0] SYNTHESIZED_WIRE_14;
wire	SYNTHESIZED_WIRE_15;
wire	[31:0] SYNTHESIZED_WIRE_17;
wire	[31:0] SYNTHESIZED_WIRE_18;
wire	SYNTHESIZED_WIRE_19;

assign	needed_an_output = SYNTHESIZED_WIRE_20;
assign	SYNTHESIZED_WIRE_2 = 1;
assign	SYNTHESIZED_WIRE_12 = 1;
assign	SYNTHESIZED_WIRE_19 = 1;


alu	b2v_ALU(.operand1(SYNTHESIZED_WIRE_0),.operand2(SYNTHESIZED_WIRE_1),.operation(operation[1:0]),.result_high(SYNTHESIZED_WIRE_17),.result_low(SYNTHESIZED_WIRE_18));

ahb_slave_sm	b2v_Control_unit(.HSEL(SYNTHESIZED_WIRE_2),.HWRITE(SYNTHESIZED_WIRE_3),.HRESETn(nreset),.HCLOCK(masterhclock),.wait_sig(SYNTHESIZED_WIRE_20),.HADDRESS(SYNTHESIZED_WIRE_5),.HBURST(SYNTHESIZED_WIRE_6),.HSIZE(SYNTHESIZED_WIRE_7),.HTRANS(SYNTHESIZED_WIRE_8),.HWDATA(SYNTHESIZED_WIRE_9),.reg_rdata(SYNTHESIZED_WIRE_10),.HREADY(SYNTHESIZED_WIRE_11),.reg_write(SYNTHESIZED_WIRE_15),.HRDATA(SYNTHESIZED_WIRE_13),.HRESP(SYNTHESIZED_WIRE_14),.reg_address(reg_address),.reg_wdata(reg_wdata));
defparam	b2v_Control_unit.ADDRESS_PHASE = 'b00;
defparam	b2v_Control_unit.BURST_PHASE = 'b11;
defparam	b2v_Control_unit.DATA_PHASE = 'b10;
defparam	b2v_Control_unit.ERROR_PHASE = 'b01;

stripe_new	b2v_inst2(.clk_ref(clk_ref),.npor(npor),.ebiack(ebiack),.intextpin(intextin),.masterhready(SYNTHESIZED_WIRE_11),.masterhgrant(SYNTHESIZED_WIRE_12),.masterhclk(masterhclock),.nreset(nreset),.ebidq(ebidq),.masterhrdata(SYNTHESIZED_WIRE_13),.masterhresp(SYNTHESIZED_WIRE_14),.masterhwrite(SYNTHESIZED_WIRE_3),.ebiaddr(ebiaddr),.masterhaddr(SYNTHESIZED_WIRE_5),.masterhburst(SYNTHESIZED_WIRE_6),.masterhsize(SYNTHESIZED_WIRE_7),.masterhtrans(SYNTHESIZED_WIRE_8),.masterhwdata(SYNTHESIZED_WIRE_9));

 //Mentor Graphics attribute b2v_inst2 NOOPT TRUE

regfile	b2v_Register_file(.reset(nreset),.clock(masterhclock),.write(SYNTHESIZED_WIRE_15),.clock_enb(SYNTHESIZED_WIRE_20),.address(reg_address[4:2]),.result_high(SYNTHESIZED_WIRE_17),.result_low(SYNTHESIZED_WIRE_18),.write_data(reg_wdata),.operand1(SYNTHESIZED_WIRE_0),.operand2(SYNTHESIZED_WIRE_1),.operation(operation),.read_data(SYNTHESIZED_WIRE_10));

wait_state_gen	b2v_Wait_state_generator(.HSEL(SYNTHESIZED_WIRE_19),.clock(masterhclock),.resetn(nreset),.HADDRESS(reg_address[4:2]),.HWDATA(reg_wdata[2:0]),.HREADY(SYNTHESIZED_WIRE_20));
defparam	b2v_Wait_state_generator.IDLE = 0;
defparam	b2v_Wait_state_generator.WAIT = 1;

endmodule

module stripe_new
(
	clk_ref,
	nreset,
	npor,
	ebiack,
	ebiclk,
	ebiwen,
	ebioen,
	ebiaddr,
	ebibe,
	ebicsn,
	ebidq,
	intextpin,
	masterhready,
	masterhgrant,
	masterhclk,
	masterhrdata,
	masterhresp,
	masterhwrite,
	masterhlock,
	masterhbusreq,
	masterhaddr,
	masterhburst,
	masterhsize,
	masterhtrans,
	masterhwdata
);

input clk_ref;
inout nreset;
input npor;
input ebiack;
output ebiclk;
output ebiwen;
output ebioen;
output [24:0] ebiaddr;
output [1:0] ebibe;
output [3:0] ebicsn;
inout [15:0] ebidq;
input intextpin;
input masterhready;
input masterhgrant;
input masterhclk;
input [31:0] masterhrdata;
input [1:0] masterhresp;
output masterhwrite;
output masterhlock;
output masterhbusreq;
output [31:0] masterhaddr;
output [2:0] masterhburst;
output [1:0] masterhsize;
output [1:0] masterhtrans;
output [31:0] masterhwdata;

endmodule

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