See Also

To specify that the FPGA Express or FPGA Compiler II software should treat the use_lpm_ram_dq.v file that you created in Example of Creating a VHDL Custom Variation of the lpm_ram_dq Function as a "black box," refer to the following code sample from the top-level design file. To modify the source code for the vhdl_design.vhd file to define the module name and port type and to specify that the module is a black box, refer to the following code sample:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY vhdl_design IS
PORT	(
	address :  IN STD_LOGIC_VECTOR  (7 DOWNTO 0);
	clock	:  IN STD_LOGIC;
	wen	:  IN STD_LOGIC;
	data	:  IN STD_LOGIC_VECTOR  (7 DOWNTO 0);
	q	: OUT STD_LOGIC_VECTOR  (7 DOWNTO 0);
	);
END vhdl_desgn;

ARCHITECTURE rtl OF vhdl_design IS

--component declaration of the "wrapper"
COMPONENT use_lpm_ram_dq
PORT	(
	address :  IN STD_LOGIC_VECTOR  (7 DOWNTO 0);
	clock	:  IN STD_LOGIC;
	wen	:  IN STD_LOGIC;
	data	:  IN STD_LOGIC_VECTOR  (7 DOWNTO 0);
	q	: OUT STD_LOGIC_VECTOR  (7 DOWNTO 0);
	);
END_COMPONENT;

BEGIN

--direct instantiation of the "wrapper"
u1: use_lpm_ram_dq
PORT MAP	(
		address => address,
		inclock => clock,
		we => wen,
		data => data,
		q => q
		);
		
END rtl;

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