See Also

The following sample shows the my_pll.vhd file, which can be generated by the MegaWizard^® Plug-In Manager as described in Example of Creating a VHDL Custom Variation of the altclklock Function. The my_pll.vhd file contains an instantiation and parameters of the altclklock function.

-- megafunction wizard: %ALTCLKLOCK%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altclklock 
-- ============================================================
-- File Name: my_pll.vhd
-- Megafunction Name(s):
-- 			altclklock
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

ENTITY my_pll IS
	PORT
	(
		inclock		: IN STD_LOGIC ;
		inclocken		: IN STD_LOGIC ;
		locked		: OUT STD_LOGIC ;
		clock0		: OUT STD_LOGIC ;
		clock1		: OUT STD_LOGIC 
	);
END my_pll;


ARCHITECTURE SYN OF my_pll IS

	SIGNAL sub_wire0	: STD_LOGIC ;
	SIGNAL sub_wire1	: STD_LOGIC ;
	SIGNAL sub_wire2	: STD_LOGIC ;



	COMPONENT altclklock
	GENERIC (
		inclock_period		: NATURAL;
		clock0_boost		: NATURAL;
		clock1_boost		: NATURAL;
		operation_mode		: STRING;
		intended_device_family		: STRING;
		valid_lock_cycles		: NATURAL;
		invalid_lock_cycles		: NATURAL;
		valid_lock_multiplier		: NATURAL;
		invalid_lock_multiplier		: NATURAL;
		clock0_divide		: NATURAL;
		clock1_divide		: NATURAL;
		outclock_phase_shift		: NATURAL
	);
	PORT (
			inclocken	: IN STD_LOGIC ;
			inclock	: IN STD_LOGIC ;
			clock0	: OUT STD_LOGIC ;
			clock1	: OUT STD_LOGIC ;
			locked	: OUT STD_LOGIC 
	);
	END COMPONENT;

BEGIN
	clock0    <= sub_wire0;
	clock1    <= sub_wire1;
	locked    <= sub_wire2;

	altclklock_component : altclklock
	GENERIC MAP (
		inclock_period => 25000,
		clock0_boost => 4,
		clock1_boost => 2,
		operation_mode => "NORMAL",
		intended_device_family => "APEX™20KE",
		valid_lock_cycles => 5,
		invalid_lock_cycles => 5,
		valid_lock_multiplier => 5,
		invalid_lock_multiplier => 5,
		clock0_divide => 1,
		clock1_divide => 1,
		outclock_phase_shift => 0
	)
	PORT MAP (
		inclocken => inclocken,
		inclock => inclock,
		clock0 => sub_wire0,
		clock1 => sub_wire1,
		locked => sub_wire2
	);



END SYN;

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