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The HDL Settings section lists all the Verilog HDL and VHDL settings for the project. The HDL settings section is used only when no EDA output tools are specified. The HDL Settings section is located in the Project Settings File (.psf).
The HDL Settings section keyword is HDL_SETTINGS.
The HDL Settings section requires a unique name, which you type as (<name>), to identify the project name.
The HDL Settings section contains statements that follow these Usage Code definitions.
The following table shows the HDL Settings section keywords (which are underscore separated), descriptions, legal settings, and usage codes:
| Keyword | Settings | Code |
|---|---|---|
VERILOG_INPUT_VERSION |
<string> (Default=Verilog_2001) | A |
VERILOG_LMF_FILE |
<file name> | A |
VERILOG_SHOW_LMF_MAPPING_MESSAGES |
On | Off | A |
VHDL_INPUT_LIBRARY |
<name> | B |
VHDL_INPUT_VERSION |
<string> | A |
VHDL_LMF_FILE |
<file name> | A |
VHDL_SHOW_LMF_MAPPING_MESSAGES |
On | Off | A |
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