| Performance
- Clk-to-Out |
| I/O Tile |
| I/O Tile |
| Tile |
| Tile |
| tINR =
0.87ns |
| tOUTR =
5.22ns |
| tLocalR =
0.3ns |
| tLocalR =
0.3ns |
| tLocalR =
0.3ns |
|
|
|
| tset = 0.62ns |
||
| thold
= 0.00ns |
||
|
|
|
| tset = 0.62ns |
||
| thold
= 0.00ns |
||
| tCLK_2_Q =
0.87ns |
| tCLK_2_Q =
0.87ns |
| tGLINR =
2.19ns |
| Hardwired
Global Network |
| tGLRR =
0.86ns +/- 0.250 (skew) |
| FMAX
= 250 MHz |
| Global Input |
|
|
|
|
|
|
|
| External Set-UP = tINR +
tLocalR + tset
- tGLINR - tGLRR |
||||||
| = 0.87ns + 0.3ns +
0.62ns - 2.19ns - 0.86ns = -1.26ns |
||||||
| Clock-to-Out
(Pin-to-Pin) |
||||||
| = tGLINR + tGLRR + tCLK_2_Q + tLocalR + tOUTR |
||||||
| = 2.19ns + 0.86ns +
0.87ns + 0.3ns + 5.22ns = 9.44ns (~105MHz) |
||||||
| These values are
worst operating conditions and best (hand) placement on a A500K130! |
||||||
|
|
| Actel ProASIC |
|
| AE Dec 99 |
|
| 40 |