Conceptually, the chip routing matrix has four major hierarchical routing levels, as shown in the Figure:
	• Ultra-fast local network--connecting a tile to its eight surrounding neighbors
	• Efficient long-line network--allowing a signal to reach one, two, or four tiles long
	• High-speed bus network--distributed throughout the chip
	• High-performance global network--with a maximum skew of 0.25 ns
	Additionally, robust power and ground grids ensure minimal supply drops and ground rises, regardless of chip pro-ramming.