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|
|
|
|
|
|
|
|
|
u |
High Efficiency
and Flexibility
|
|
|
|
l |
Nearly double the
routing switches of SRAM PLDs
|
|
|
|
l |
Higher
utilization of routing resources
|
|
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|
l |
Enables ASIC-like
timing and utilization predictability
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l |
Pin-fixing at up
to 90% utilization
|
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|
l |
Shorter segments
consume less power
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|
u |
High Performance
Routing Hierarchy
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|
|
l |
Regular structure
for block-level design
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|