| Flexible
Design Flow |
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| High Level |
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| Design Description |
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| (VHDL, Verilog) |
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| Functional |
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| Simulation |
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| ActGen |
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| Macro
Genrator |
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| Synthesis |
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| Tool |
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| EDIF,
Verilog, and |
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| VHDL interfaces |
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| coupled
with standard |
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| library
formats allow |
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| easy
integration into |
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| the most
integrated |
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| ASIC
design flows |
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| Forward Timing |
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| Constraints (SDF) |
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| Structural Netlist |
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| (EDIF, VHDL, Verilog) |
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| Placement/Floorplan |
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| Constraints |
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| MEMORYmaster |
| ASICmaster |
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| SDF Timing |
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| File |
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| Programming |
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| Data |
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| Silicon |
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| Sculptor |
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| FlashTimer: |
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| Timing Analyzer |
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| Timing |
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| Simulation |
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| Silicon |
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| Explorer II |
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| Actel ProASIC |
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| AE Dec 99 |
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| 24 |