Meeting the System-Level Challenge
			u FPGA and ASIC Tool Flow Supported Equally Well l Push button flow: Synplicity / Exemplar / Synopsys l First seamless ASIC flow with Synopsys / Cadence (Ambit) n Easy ASIC migration n No new learning curve on tools n Highly predictable timing (wireload model) n Timing-driven synthesis and P&R actually work and work together u IP Friendly l IP protection and licensing capability l Vast majority of RTL IP existing today is optimized for gates
	Actel ProASIC AE Dec 99
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