| Superior
Silicon by Design |
| ˇ°Easy
Migrationˇ± |
| ˇ°Design
Flowˇ± |
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| Methodology |
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| • ASIC |
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| • FPGA |
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| Methodology |
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| • IP friendly |
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| • ASIC Flow |
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| ˇ°Predictabilityˇ± |
| ˇ°Gatesˇ± |
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| Architecture |
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| • Low Power |
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| • High Performance |
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| Architecture |
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| • Fine-Grained |
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| • Segmented routing |
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| ˇ°ISPˇ± |
| ˇ°Single
Chipˇ± |
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| Process |
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| • Small element |
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| • Re-programmable |
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| • High Volume |
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| Flash |
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| • Non-Volatile |
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| • Secure |
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| • Very Compact |
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| Concept |
| Reality |
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| Actel ProASIC |
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| AE Dec 99 |
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| 37 |