A500K ProASIC™ Family

The First Programmable Device Optimized for Gate Array Designers

“All things being equal, I would use a programmable device over a masked device”

- anonymous engineer

What Is ProASIC?

0.25u 4LM Flash-Based CMOS Programmable Device

Re-programmable and non-volatile

Live at power-up

Cost effective, single-chip solution

Fine Grained Architecture

Predictable performance and high utilization

Flip-flop rich

Ideal for ASIC or FPGA design flows

Designed for IP re-use

1/3 - 1/2 the power of LUT-based PLDs

Embedded Memory/FIFO Blocks

Design and IP Security Features*

ProASIC Flash Switch

Fine Grain Advantage

Architecture Overview

ProASIC Logic Cell: The Tile

Homogeneous Array of Advanced Fine-Grained Cells

Very efficient utilization

High speed

ASIC-like-- works well in ASIC tool flow

IP-friendly -- closest thing to a gate

Embedded Memory

Dual-Port SRAM and FIFO Capability

1R/1W 256 x 9 embedded memory blocks: cascadable

Up to 133 MHz synchronous and asynchronous operation

FIFO Control Logic: First with ProASIC

Decoder, control and flag circuitry

Parity generation and detection logic

Access and cycle time 7.5ns

MEMORYmaster^TM Tool
Automates Memory Generation

Parameters and configuration
fully programmable

ProASIC Routing

High Efficiency and Flexibility

Nearly double the routing switches of SRAM PLDs

Higher utilization of routing resources

Enables ASIC-like timing and utilization predictability

Pin-fixing at up to 90% utilization

Shorter segments consume less power

High Performance Routing Hierarchy

Regular structure for block-level design

ProASIC Routing Hierarchy

Four High-Speed Globals

High-Performance Routing Hierarchy

Corner-to-Corner Delay
< 4ns (typical)

Ultra-fast Local Routing

High-Speed Bus Network

Efficient Long Line Routing

ProSELECT I/Os

ProASIC Performance

Predictable High-Performance

ProASIC Programming

Device Programming through Standard JTAG

Silicon Sculptor & Silicon Explorer II

On-board programming (ISP) through 26-pin header

JTAG inputs re-definable as user I/Os for operation

Package Availability

ProASIC Power Advantage

Meeting the System-Level Challenge

FPGA and ASIC Tool Flow Supported Equally Well

Push button flow: Synplicity / Exemplar / Synopsys

First seamless ASIC flow with Synopsys / Cadence (Ambit)

Easy ASIC migration

No new learning curve on tools

Highly predictable timing (wireload model)

Timing-driven synthesis and P&R actually work and work together

IP Friendly

IP protection and licensing capability

Vast majority of RTL IP existing today is optimized for gates

ASICmaster™ Software

Hierarchical Place & Route

Based on multi-million gate ASIC P&R system

Push-button and interactive

Timing-driven place and route

Incremental design flow supports ASIC-like “ECO”

MEMORYmaster™

Verilog or VHDL (Output for Synthesis and Simulation

Power Estimator

Accuracy to ~15% of final

Layout Viewer

Allows for quick isolation of problem nets

Standard Links to industry standard EDA Tools

Flexible Design Flow

ASICmaster™ Software

Using the Layout Viewer

ProASIC for IP Market

Implementation

Almost no re-design of IP is required (memory implementations)

Significantly lower investment from IP vendors

Compatibility with ASIC Flow

Ensures core availability

Allows use of soft IP

Support for IP Vendor Business Model

Design security features ensure a high degree of protection

Unique licensing capability to support IP vendor

Allows IP to be licensed to a given # of devices

Follows the “royalty” model developed by ASIC community

Factory programming further protects IP

ProASIC for the Logic Designer

Allows Customer to Delay Silicon Choice

Let logic designers be logic designers

Preserves Investment in Chosen Tools and Training

Simplifies Design Re-Use Challenges

Simplifies Board-Level Issues

Lower Power consumption

Single chip

Non-volatile and re-programmable

Live at power-up

Looking Ahead

SRAM Products are Maturing

Less architectural innovation

Leader on the process curve wins most designs

ProASIC is Just Getting Going

Full support of floor planning

Increased performance

Roadmap to 2+ million system gates on .22u embedded Flash

HARD IP

3X improvement in P&R runtimes

Special I/O features

Internet upgradeable configuration

ProASIC: Comparing Options

The Best of Both Worlds

Availability

ProASIC Back-up Slides

The Actel / Gatefield Partnership

Memory Configurations

Superior Silicon by Design

Flash = Small Die

ProASIC vs. Virtex Die Size

Performance - Clk-to-Out

Next - ProASIC II

ProASIC II

Next generation standard ProASIC product family

Planned features

Architectural enhancements

PLL and differential I/Os

More convenient programming through the Internet

Why another 0.25µ / 0.22µ Product Family ?

Process technology roadmap ain’t that easy anymore

System supply voltage adoption

Exploit density and cost advantage of ProASIC technology

Focus on system level integration

It’s no longer just: bigger, cheaper, easier, faster …

Key ProASIC II Features

Performance

Full 66MHz, 64bit PCI capability

Enhanced IO Capabilities

LVDS and LVPECL

PCI, GTL, GTL+

SSTL, HSTL

Increased Productivity

P&R: 10 x AM5

Block reuse and predictability over whole product range

Support of embedded functional blocks

Improved Ease of Use

Enhanced ISP interface for remote upgrades

ProASIC II Schedule

Goal is for 1.5M “System Gates”

Pin compatible within family

Voltage and GND pins compatible with 500K

Gate counts interleave existing 500K products

First sampled Silicon expected end of 2000


	The First Programmable Device Optimized for Gate Array Designers


	0.25u 4LM Flash-Based CMOS Programmable Device
		Re-programmable and non-volatile
		Live at power-up
		Cost effective, single-chip solution
	Fine Grained Architecture
		Predictable performance and high utilization
		Flip-flop rich
		Ideal for ASIC or FPGA design flows
		Designed for IP re-use
		1/3 - 1/2 the power of LUT-based PLDs
	Embedded Memory/FIFO Blocks
	Design and IP Security Features*


	Homogeneous Array of Advanced Fine-Grained Cells
		Very efficient utilization
		High speed
		ASIC-like-- works well in ASIC tool flow
		IP-friendly -- closest thing to a gate


	Dual-Port SRAM and FIFO Capability
		1R/1W 256 x 9 embedded memory blocks: cascadable
		Up to 133 MHz synchronous and asynchronous operation
	FIFO Control Logic: First with ProASIC
		Decoder, control and flag circuitry
		Parity generation and detection logic
		Access and cycle time 7.5ns
	MEMORYmaster^TM Tool Automates Memory Generation
		Parameters and configuration fully programmable


	High Efficiency and Flexibility
		Nearly double the routing switches of SRAM PLDs
		Higher utilization of routing resources
		Enables ASIC-like timing and utilization predictability
		Pin-fixing at up to 90% utilization
		Shorter segments consume less power
	High Performance Routing Hierarchy
		Regular structure for block-level design


	Four High-Speed Globals
	High-Performance Routing Hierarchy
	Corner-to-Corner Delay < 4ns (typical)


Device Programming through Standard JTAG
	Silicon Sculptor & Silicon Explorer II
		On-board programming (ISP) through 26-pin header
	JTAG inputs re-definable as user I/Os for operation


FPGA and ASIC Tool Flow Supported Equally Well
	Push button flow: Synplicity / Exemplar / Synopsys
	First seamless ASIC flow with Synopsys / Cadence (Ambit)
		Easy ASIC migration
		No new learning curve on tools
		Highly predictable timing (wireload model)
		Timing-driven synthesis and P&R actually work and work together
IP Friendly
	IP protection and licensing capability
	Vast majority of RTL IP existing today is optimized for gates


	Hierarchical Place & Route
		Based on multi-million gate ASIC P&R system
		Push-button and interactive
		Timing-driven place and route
		Incremental design flow supports ASIC-like “ECO”
	MEMORYmaster™
		Verilog or VHDL (Output for Synthesis and Simulation
	Power Estimator
		Accuracy to ~15% of final
	Layout Viewer
		Allows for quick isolation of problem nets
	Standard Links to industry standard EDA Tools


Implementation
	Almost no re-design of IP is required (memory implementations)
		Significantly lower investment from IP vendors
Compatibility with ASIC Flow
	Ensures core availability
	Allows use of soft IP
Support for IP Vendor Business Model
	Design security features ensure a high degree of protection
	Unique licensing capability to support IP vendor
		Allows IP to be licensed to a given # of devices
		Follows the “royalty” model developed by ASIC community
		Factory programming further protects IP


	Allows Customer to Delay Silicon Choice
		Let logic designers be logic designers
	Preserves Investment in Chosen Tools and Training
	Simplifies Design Re-Use Challenges
	Simplifies Board-Level Issues
		Lower Power consumption
		Single chip
		Non-volatile and re-programmable
		Live at power-up


	SRAM Products are Maturing
		Less architectural innovation
		Leader on the process curve wins most designs
	ProASIC is Just Getting Going
		Full support of floor planning
		Increased performance
		Roadmap to 2+ million system gates on .22u embedded Flash
		HARD IP
		3X improvement in P&R runtimes
		Special I/O features
		Internet upgradeable configuration


ProASIC II
	Next generation standard ProASIC product family
	Planned features
		Architectural enhancements
		PLL and differential I/Os
		More convenient programming through the Internet
Why another 0.25µ / 0.22µ Product Family ?
	Process technology roadmap ain’t that easy anymore
		System supply voltage adoption
	Exploit density and cost advantage of ProASIC technology
	Focus on system level integration
		It’s no longer just: bigger, cheaper, easier, faster …


	Performance
		Full 66MHz, 64bit PCI capability
	Enhanced IO Capabilities
		LVDS and LVPECL
		PCI, GTL, GTL+
		SSTL, HSTL
	Increased Productivity
		P&R: 10 x AM5
		Block reuse and predictability over whole product range
		Support of embedded functional blocks
	Improved Ease of Use
		Enhanced ISP interface for remote upgrades


Goal is for 1.5M “System Gates”
	Pin compatible within family
		Voltage and GND pins compatible with 500K
	Gate counts interleave existing 500K products
First sampled Silicon expected end of 2000