EEL 4783: Hardware/Software Co-design with FPGAs

 

 

Course:


EEL 4783: Hardware/Software Codesign with FPGAs, Spring 2012. 3 credits.

Lectures: MW9.00-10:15AM @ HEC 110

               Instructor Office Hours: MW 10:15-12:00AM @ HEC 416

               TA office hour: W 11:00AM-1:00PM@Eng. I Building, Room471


Course Instructor:


Mingjie Lin

Office: HEC 416, Telephone: 407-882-2298

Email: mingjie@eecs.ucf.edu, Home Page: http://www.eecs.ucf.edu/~mingjie


               TA: ashok khanal ashok@knights.ucf.edu

Course Description:


This course provides a systematic introduction to the topic of Hardware-Software Codesign. It emphasizes the basic ideas, and the practical aspects of Hardware-Software Codesign with FPGA devices. In addition, this course presents techniques for modeling hardware and software components at different levels of abstraction and many concepts including the various forms of expressing computations, sequential and parallel implementations, control-flow and data-flow, control dependency and data dependency, latency and throughput as well as the architecture design space of hardware data paths, finite state machines, micro-programmed machines, instruction-set processors, system-on-chip, and on-chip buses. Specific topics include:

•     Analyzing the control-flow and data-flow of a software program and a cycle-based hardware description

•     Transforming simple software programs into cycle-based hardware descriptions with equivalent behavior and vice versa

•     Partitioning simple software programs into hardware and software components, and creating appropriate hardware-software interfaces to reflect this partitioning

•     Identifying performance bottlenecks in a given hardware-software architecture and optimize them by transformations on hardware and software components

•     Using simulation software to co-simulate software programs with cycle-based hardware descriptions.

 

Prerequisites:

EEL 3342: Digital Logic Design

 

Co-prerequisites:

EEL 4768: Computer Architecture

 

Minimally Required Skills:

Basic logic design, basic HDL (Verilog or VHDL) programming, basic software programming skills.

 

Recommended Text:

“A Practical Introduction to Hardware/Software Codesign", Patrick Schaumont, Springer, 2009


Grading:


The distribution of weights for the exams, assigments, and projects is as follows:

 

Midterm Exam

20%

Final Exam

30%

Projects

30%

Assigments

20%

 

Students are encouraged to participate in class.

 

Honor System Policy:


Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course

 

Schedule (minor changes possible throughout the semester )

Event Spring 2012 Topics Notes Assignments
Lecture 1 Jan 9
 Introduction (Objectives, Expectations, Logistics) pdf
Lecture 2 Jan 11 Hardware vs. Software
 pdf 1. Download SystemC lib
2. Download SystemC tests
3. Install both on your own PC
MLK day Jan 16


Lecture 3 Jan 18
 Overview: Digital Camera
 pdf 1. HW1. Coding assignment.
2. Read Essential C from Stanford CS Education Library.
3. Read Unix programming tool from Stanford CS Education Library.
Lecture 4 Jan 23 Digital Camera: Software Implementation
 pdf 1. Software implementation of a digital camera: digcam.zip
2. HW2
Lecture 5 Jan 25
 Digital Camera: Software Implementation
pdf

1. Programming Assignment 1 out, due in two weeks.
Lecture 6 Jan 30
Lecture 7 Feb 1
 Introduction to Basic C/C++ Programming
 pdf 1. HW3 out. HW2 due today.
Lecture 8 Feb 6
Project code review 1

Lecture 9 Feb 8
 Project code review 2. Verilog Introduction. pdf Verilog according to Tom.
Lecture 10 Feb 13

VHDL Introduction.

 pdf

VHDL tutorial 1. VHDL tutorial 2.
Lecture 11 Feb 15
Lecture 12 Feb 20 Hardware Implementation of CODEC (Huffman Decoder)

 pdf
1. Programming Assignment 1 Due.
2. Programming Assignment 2 out, due in two weeks.
3. Src Code of PA2.
4. code.
Lecture 13 Feb 22
Lecture 14 Feb 27 HW/SW Partitioning
 PA2 Timing graph updated
Lecture 15 Feb 29
 Huffman Decoder Programming Project: Q&A
 Xilinx FSM
 1. PA2 Timing graph updated
2. Programming Assignment 2
3. code.
Spring Break Mar 5


Mar 7

1. Sample Mid-Term
Lecture 16 Mar 12 Pipelined Processor: Design and Implementation
 pdf
Lecture 17 Mar 14 Mideterm Exam
1. PA2 Due today!
Lecture 18 Mar 19
PA2 and Midterm
 pdf 1. Midterm
Lecture 19 Mar 21 Introduction to SystemC
 pdf
 1. Instructions of installing SystemC
2. HW3: install SystemC and compile the hello.c. Email the output to the TA. Due on March 28.
Lecture 20 Mar 26 Demo of Install VirtualBox, SystemC, and Compiling.
1. PA3 Part 1:
Download the Verilog source code. Simulate it without any modification. Send the simulation output to TA by Apr 2.
Lecture 21 Mar 28
 SystemC Data Types, Methods, and Debugging
 pdf 1. Quick References of SystemC.
Lecture 22 Apr 2
 System-Level Modeling in SystemC 2.0
 pdf 1. PA3 Part 2:

a) Compile and run C++ program imageEdgeDetector.cpp of edge detection algorithm, try to understand the program in general, at least to find 4 steps of the program.

b) To compile you need to type in terminal window:
g++ -o [output name] [file name]

c) To run: ./[output name]

example image: goldenbridge
Lecture 23 Apr 4
 Describing Synthesizable RTL in SystemC
 pdf
Lecture 24 Apr 9
 Describing Synthesizable RTL in SystemC (cont.) pdf 1. PA3 Part 3: We would like to make some simple co-design of the algorithm given above (imageEdgeDetector.cpp). We divide it into 2 parts (Software and Hardware). Let the software part “SW” read and write picture from/to a file and hardware “HW” makes all the calculations for the algorithm. Lets store the picture read as input into some common memory, the same story goes for calculated picture (this means we would have some global matrixes of pictures as unsigned char* inputImage). Make 2 clocked modules in SystemC: “SW” and “HW” and establish communication between them with the help of ready signals, for example such as inputPictureReady and outputPictureReady.

a) Download the startup SystemC file [link].
b) Replace two functions  and in imageEdgeDetector.cpp with SystemC implementation.
c) Your implementation should produce exactly the same output image as in the Part 2.
Lecture 25 Apr 11 Hardware-Software Co-Simulation
 pdf
Lecture 26 Apr 16
pdf
Lecture 27 Apr 18
pdf PA3 Part3 Due.
Lecture 28 Apr 23 Final Exam Preparation


Final Exam
Apr 25Location: Classroom HEC 110, Time: 8:00-10:00AM
Assignments and Projects:

 1. Homework assignment will be weekly and programming project will be bi-weekly.

2. In the first half of this semester, we will prepare you with two small C programming assignments, two small Verilog programming assignments, and two SystemC programming assignments. Each of the small programming assignments will be independent. In the second half of this semester (after spring break), we will do a large project.

3. For the large project, we will implement a Digital Camera using both software and hardware (of course much simplified). Everything will be based on software modeling. The large project will be divided into 4 sub-projects: a)  a pure software implementation. b) identiying the performance bottleneck within the software implementation. c) replace the performance-critical part with a hardware implementation in SystemC. d) finally, we use Verilog to replace SystemC implemention. Each sub-project will be finished in two weeks.

4. All programming assignments will not be from scratch, meaning that we will give you an incompelte implementation and students needs to add their own implementation to complete the implementation.

5. In class, we will review basic C/C++ programming and Verilog programming. We will not assume any prior SystemC exposure and will teach you SystemC programming from ground up.