This page documents a DLX implementation done by the Microsystems Prototyping Laboratory(MPL) housed at the MSU Engineering Research Center. The implementation was used as a design driver to help validate the MPL SCMOS and GCMOS standard cell libraries . We make no claims as to the quality of this implementation. The implementation has been tested via an extracted transistor-level netlist simulation; pictures of sample layouts can be seen here . No layouts have been fabricated. Our implementation differs somewhat from the implementations found in the Hennessey and Patterson Computer Architecture textbooks. One major change is that we changed the encoding of the shift instructions so that the immediate value is stored in the same field as immediates for other instructions; we also added some interrupt capabilities. Because of this, the distribution includes a modified version of dlxsim which is used to produce the object code file read by the VHDL simulation. This implementation was actually done several years ago in the Mentor/GDT 'M' modeling language when the first H&P textbook appeared ( A Quantitative Approach ). In fall 1996, the M language implementation was converted to VHDL. As such, the signal names and block diagram structure do not match the implementation structure found in the newer H&P textbook ( The Hardware/Software Interface , which documents a MIPS implementation). Our implementation's control structure could definitely be further streamlined and improved. This implementation has served its purpose, however, in providing a non-trivial test case for our standard cell libraries.

• VHDL Heirarchical Model for DLX Implementation

• DLX Datapath

• Major functional modules of DLX Processor
  
  • DLX ALU

  • DLX 32x32-bit Register File

  • DLXREGS

  • PC

• Signal Documentation of VHDL Codes for DLX

• VHDL Simulation of DLX Microprocessor

• Other DLX Links

Send comments, suggestions to reese@erc.msstate.edu