Control flow: One hot (Shift) controllers

Synchronous controllers

This is a variation on the theme of controllers from the last lecture. By simply specifying the encoding for each state

"0001 0010 0100 1000"  etc.

we force the synthesizer to implement the FSM as a one-hot controller.


For the general case, it would appear that two levels of logic between flipflop outputs and inputs is still required. However, "one-hot" controllers usually reduce the combinational logic between stages, resulting in a faster controller with more flipflops but less logic. The two equivalent multiphase clock generator circuits shown below are an example.

FSM implementation

One Hot implementation
It is desirable to be able to treat a VHDL process as an Algorithmic State Machine (ASM). This leads to multiple WAIT statement in processes that separate the blocks of action into separate separate states. We may continue to show state explicitly. e.g.

current_state <= "0001"

The number of WAIT statements determines the number of states we have in this machine. It is natural to view the process with its multiple WAIT statements as an algorithmic state machine (ASM).

	-- input / output actions in the initial state
WAIT UNTIL the criteria for transition to the next state are satisfied;
	-- input / output actions for state 2
WAIT UNTIL .......

Example: An alternative form of process statement representing the counter circuit of the FSM from the last lecture is:

process
-- initial state.
current_state <= "0001"
Z <= X;
wait until (clock'event and clock = '1') and X = '1';
current_state <= "0010"
Z <= X;
wait until (clock'event and clock = '1') and X = '1';
current_state <= "0100"
Z <= X;
wait until (clock'event and clock = '1') and X = '1';
current_state <= "1000"
Z <= '0';

where the SynchCkt is:

Note, however, that such a model poses some difficulties for the synthesizer in analyzing:
1. It suggests that the primary input X should somehow be ANDed into the clocking input. As the schematic for the example above shows, it should steer the primary input (either D or J / K).

   The X is ANDed after the transition when if it really fed the clock input to a flipflop, the clock transition would be sensitive also to the X input rising. In the next section we attack this problem.

2. The synthesizer must infer the feedback required to hold the machine in the same state when a clock transition occurs and the UNTIL condition is not satisfied.

   Note that for the example above most of the combinational logic involved is for the purpose of keeping the D flipflop from resetting on the next clock while X='0'.

3. The redundancy in the WAIT statements somehow needs to be optimized out of the design.

Factoring the condition expression into (transition_expression) AND (stable_expression)

1. Transition expression

   For example, clock'event and clock = '1'. The 'event tells the analyzer that this literal needs to be part of the transition expression. Every other part of the expression that contains the same literal (in this example, clock) must also be included in the transition expression.

2. Stable expression

   The rest of the literals should go into the stable expression. Nevertheless, this form is useful for understanding the design of asynchronous one-hot controllers in the next section.

Special note not covered in class lecture.

Notice that theUNTIL expression for the counter circuit above is evaluated both when a transition occurs on the clock and on X. Consider the following variations on the resulting circuits to be synthesized:

WAIT UNTIL clock = '1' and X='1';

means that we must assume the D flipflop marking the state can be set by a clocking transition on either the clock or X.



WAIT UNTIL clock'event and clock = '1' and X='1';

means that evaluation of the expression at X changing to '1' must always be false unless it coincides with the clock transition. Therefore X is part of the stable expression and clock is in the part of the transition expression that determines if the edge is rising or falling.



WAIT on clock UNTIL clock = '1' and X='1';

means that evaluation of the UNTIL expression will occur only on clock transitions. The synthesis tool still needs to recognize that "clock = '1'" is part of the transition expression, and treat only the X='1' term as the stable expression.

Implicit State

When we treat a VHDL process as an Algorithmic State Machine (ASM), we make the notion of "state" coincide with the notion of "point of execution" of an algorithm. Just as we do not keep track of the value of the program counter explicitly in executing programs, we would prefer not to have to keep track of the "state" explicitly as we work our way through the process. That is, the synthesizer should produce the next state logic and state flipflops implicit in the ASM represented by the process description. This is especially useful when we begin to build asynchronous controllers.

Rev. 9/16/95 B. Huey