Behavioral VHDL constructs and structural equivalents #2

Synthesis of variables as signals.

• Input to output definition of functional behavior.
• Variable assignment statements become ordered wiring lists.
• Note that the timing remains lumped with the signal assignment statement(s) at the bottom.

  Example:

  	architecture aa of ee is
  		signal x, y, sum, cin, cout : bit;
  	begin
  	adder:  process (x, y, cin)
  		variable p, g;
  	begin
  		p := x xor y;
  		g := x and y;
  		sum <= cin xor p after tsum;
  		cout <= cin and p or g after tcarry;
  	end process;
  

  

For loops

• Synthesize logic iteratively in space, not time.

  Example: the N-input AND gate

  	lb0:  process (x)
  		variable result : bit ;
  	begin
  		result := '1';
  		for i in x'range 
  		loop
  			if x(i) = '0' then
  				result := '0';
  				exit;
  			end if;
  		end loop;
  
  	end process;
  

By eliminating all AND gates with an input that is always '0', all AND inputs that are always '1', and all OR inputs that are always '0', we end up with the following circuit:



After collapsing inputs and balancing them, we can produce an N-input AND gate.

Suppose the loop boundaries are dynamic: Example: FOR i in vleft to vright LOOP

1. The amount of logic to be replicated (in space) to implement the content of the loop in parallel is variable, and the synthesis will have to implement using the minimum value of vleft and the maximum value of vright.
2. Since the indexing process cannot be given a static interpretation, selector logic must be implemented to allow dynamic interpretation of the value of the index in the hardware itself. An expression such as X(i) will require that it be possible to route the value from any bit of vector X in the range of values i can assume to some destination.

   WAIT statements

   Most tools require that there be only ONE WAIT statement per process

   1. to produce synchronous circuits
   2. to produce finite state machines (FSMs)
   3. to allow straightforward differentiation between combinational and sequential circuits

   Sensitivity lists

   require no direct synthesis generally. A single sensitivity list, whether in the process statement itself, or in a WAIT statement in the body of the process, should indicate all the signals appearing on the right hand side of statements in the process. The implementation can consist entirely of combinational logic.

   UNTIL conditions in a WAIT statement

   require the synthesis of either flipflops or latches. Note that while a process is WAITing, simulation time is changing and this implies that the signals updated following the WAIT statement retain whatever current value they have. I.e., they exhibit memory.

   If the condition expression includes sig'EVENT, it represents a clocking action that will be implemented with a flipflop or clocked register.

   If the condition expression does not include sig'EVENT, it represents an enabling action for a register.

   FOR time

   No direct synthesis generally. Implementation of such a construct would either imply crude time approximations that would be realized with a one-shot, or suggests the use of a timer circuit driven from a clock. Such a timer circuit would call for a more elaborate implementation and knowledge of the clock cycle time for the timer input than should be inferred from such a simple WAIT statement as this.

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   Copyright 1995, Ben M. Huey
   Copying this document without the permission of the author is prohibited and a violation of international copyright laws.

   Rev. 9/6/95 B. Huey