Concurrent VHDL constructs and structural equivalents #1

Waveforms

Concurrent signal assignments may prescribe not only one signal updating event, but many. The general form is

sig_identifier <= val_expr after delay { , val_expr after delay } ;

where the curly brackets mean the enclosed part may be repeated any number of times.

Synthesis tools generally require that only single events be specified for waveforms. No general mechanism for synthesizing waveform sequences exists.

Conditional signal assignment (When-else statements)

Simple when-else

	S <= Wa when c0 else Wb ;




	

More complex when-else statements imply priority encoding.



S <= 	W0 when c0
	W1 when c1
	W2 when c2 
	else Wx ;



	

Note: Priority encoding is required when more than one condition might be true at the same time. VHDL rules that the condition appearing first in the statement has the priority.

No ELSE implies Memory

	S <= X when C ;

Memory is implied where no else clause is provided. In the simulation model, no event is implied when the condition is false, so the signal retains its old value. I.e., it has memory.

Examples:

	Q <= D when rising_edge (clock);

	B <= A when phase_a = '1' ;
		

Simple enabling requires

	-- for simple AND enabling
	B <= A when enable else ( others => '0');  

	-- for tri-state driver output
	B <= A when enable else ( others => 'Z');  
		

Selected signal assignment statements

• All values must be included

  Therefore, the range of values for the selector must be restricted

  For example, a useful selector might be

  type ccodes is  (uncond, zero, less, lteq, never, nzro, gteq, grtr );
  	signal cc : ccodes;
  	...
  	with cc select ....
  	

  On the other hand, a declaration

  signal csel : integer;

  could call for a 2**32-1 sized multiplexer. This is hardly something we would want to build! Even where address decoding is required the range should be 0 to 255 or so, the address partitioned to correspond to the decoding method being used.

• Since no more than one value to be selected at a time, so no priority encoding is involved.

  Example: Consider a simplified branch condition selector for a microprocessor. Typically the cond of the instruction specifies which of several logical expressions of status flipflops is to be used.

  With IR_cond  select
  		branch  <= '1'	when uncond ,
  		Z  	when zero ,
  		S xor V 	 when less ,
  		(S xor V) and Z  when lteq ,
  		'0'  	when never ,
  		not Z  	when nzro ,
  		not(S xor V)  	when gteq ,
  		not(S xor V) and Z  when grtr ;
  
  	

  

  OTHERS clause may be used

  handing 'X' -- draft standard

  unused inputs

  optimization possibilities

Translation of a simple concurrent ALU example into structure.

USE work.std_logic_1164.all;

ENTITY ALU is

-- Generic delays, with default values
generic (  cout_delay:  time := 3 ns;	-- carry out delay
	   reg_delay:  time := 8 ns); 	-- register delay

-- IO ports

port  (		-- Data Out (latched)
	dout:	out std_logic_vector;

		--  A leg and B leg inputs
	a, b:	in std_logic_vector;

		-- Carry in, 1 bit
	cin:	in std_logic;

		-- Carry Out, 1 bit, unlatched		
	cout:	out std_logic;

		-- Function select (2 bits)
		--	00 ==> ADD
		--	01 ==> OR
		--	10 ==> AND
		--	11 ==> XOR
	func_sel:	in std_logic_vector (0 to 1);

		-- Result register clock (rising edge)
	clk:	in std_logic);

end ALU;

Notes:
1. The generic delays are given default values here. However, when this entity is inserted into a higher level architecture as a component, it is possible to override these values.

2. We deliberately have not specified the width of the ALU. It is to be determined at BUILD time from the width of the signal paths connected to inputs a, b, and output dout. These should all be of the same width, so it would be appropriate to add an assertion statement here that checks for that. Such an assertion would be checked only at initialization, and does not produce anything for synthesis.

USE work.ALU_funcs.add_w_carry;

ARCHITECTURE concurrent of ALU is

	constant XOUT:  std_logic_vector(0 to dout'length) := (others=>'X')

	-- ALU output:  carry concatentated to left end makes an extra bit
	signal ALUout:  std_logic_vector(0 to dout'length);	
	signal ResReg:  std_logic_vector(0 to dout'length) register;	

-- Opcode interpretation
	constant OPADD:	std_logic_vector := "00";  
	constant OPOR:	std_logic_vector := "01";
	constant OPAND:	std_logic_vector := "10";
	constant OPXOR:	std_logic_vector := "11";

begin
	with func_sel select
		ALUout <= '0' & (a OR b) 	when OPOR,
		 	'0' & (a AND b) 	when OPAND,
			'0' & (a XOR b) 	when OPXOR,
			add_w_carry(a,b,cin) 	when OPADD,
			-- where add_w_carry returns a value
			-- one greater than the size of its inputs 
			XOUT	when OTHERS;

reg_clk:  block (rising_edge(clk))
	begin
		ResReg <= guarded ALUout(1 to dout'length);
	end block;

	cout <= ALUout(0) after cout_delay;
	dout <= ResReg after reg_delay;

END concurrent;

Rev. 9/8/95 B. Huey