VHDL does not support physical dimension very well -- but that is what synthesis must map the design to. Vendor supplied and user-specified attributes help to make VHDL adequate for mapping to the physical dimension of design.
It is extremely important to ensure that
Note that simulation occurs on the behavioral axis. Even structural models (e.g. netlists) have to be interpreted behaviorally by event protocols on the nets themselves, and by procedural models of the elements (e.g. gates and flipflops) being simulated.
Example: Replacing a procedural description of the operations to be performed by an ALU with the structure for the ALU.
Example: substituting the gate level description for the MSI symbol of a multiplexor)
Example: replacing integer range 0 to 255 with std_logic_vector ( 7 downto 0)
It is critically important that as the design proceeds to increasing detail and from behavioral axis => structural axis => physical design that changes to the specification be reflected back into the more abstract models of the initial design.
This is especially important in adding detail to the design: e.g. synchronization and timing, back annotation as drive capabilities and path delays are determined.
Rev. 8/31/95 B. Huey