VHDL'96 HOMEWORK ASSIGNMENTS :
Copyright © 1993 by McGraw-Hill, Inc. and Zainalabedin Navabi
Last updated 12/01/96 by Funda Kutay.
Please let me know if you see a spelling or any kind of mistakes.
Thank you.
Funda.
HOMEWORK SET - 1 :
3.2) Write a dataflow description for a Full Adder
3.3) Wire 4 full adders to build a nibble adder.
3.5) Write a behavioral description for the Sequence Detector to
detect 101 sequence.Your sequence should detect overlapping
sequences.
3.6) Write a procedure for converting integers between 0 and 255
to a byte.
HOMEWORK SET - 2 :
4.1) Write VHDL descriptions for a two-input NOR gate and an
XOR gate. Use single delay models similar to ones used in
Section 4.1. Use 4 ns and 7 ns delays for the NOR and XOR
repectively. Use inertial delays.
4.6) Write a VHDL description for a package of four NAND gates,
using single_delay model for each of the gates. Use the
following entity decleration.
ENTITY four_nand2
IS PORT (
i1_a, i2_a, i1_b, i2_b,
i1_c, i2_c, i1_d, i2_d : IN BIT;
o1_a, o1_b, o1_c, o1_d : OUT BIT);
END four_nand2;
4.7) Use four_nand2 package of Problem 4.6 to describe a clocked
SR latch. The solution to this problem depends on code
developed in 4.6.
4.8) The following description uses the four_nand2 package of
Problem 4.6. What Boolean function this description
implementing? The solution to this problem depends on
code developed in 4.6.
ENTITY unknown IS PORT (a, b, c, d : IN BIT; z : OUT BIT);
END unknown;
--
ARCHITECTURE mystry OF unknown IS
COMPONENT chip PORT (
i1_a, i2_a, i1_b, i2_b,
i1_c, i2_c, i1_d, i2_d : IN BIT;
o1_a, o1_b, o1_c, o1_d : OUT BIT);
END COMPONENT;
FOR ALL : chip USE ENTITY WORK.four_nand2 (packing);
SIGNAL i1, i2, i3 : BIT;
BEGIN
g1 : chip PORT MAP (a, b, c, d, i1, i2, i3, i3, i1, i2, i3, z);
END mystry;
4.10) Using only XOR gate models of Problem 4.1, write a VHDL
description for an 8-bit even/odd parity checker. The
circiut has an 8-bit input vector and two outputs. The odd
output is to become 1 when the number of 1s in the input
in odd. The even output is the opposite of the odd output.
Use generate statement(s). The solution to this problem
depends on code developed in 4.1.
4.15) Write a VHDL description for a master-slave JK flip-flop.
Use the fast_single_delay model of nand2 to avoid
oscillation. In addition to this gate, you can use all
gates in Section 4.1.
4.16) Use JK flip-flop in Problem 4.15 to design a 1-bit modular
binary counter. Based on this module, build a 4-bit binary
ripple up-counter. Design this counter such that it can
easily be cascaded for building large counters. The
solution to this problem depends on code developed in 4.15.
HOMEWORK SET - 3 :
5.1) Write a function for the carry output of a full-adder.
5.2) Write a function for the sum output of a full-adder.
5.4) Using the carry and sum functions of Problems 5.1 and 5.2,
write a functional description of a full-adder. Use an
entity decleration with a, b, and ci inputs and s and co
outputs. In the functional architecture of this entity
include the necessary functions. Use 21 ns and 18 ns
delays for the sum and carry outputs respectively. The
solution to this problem depends on code developed in
Problems 5.1 and 5.2.
5.18) Write a procedure that assigns consecutive binary numbers to
its OUT BIT_VECTOR lines. The parameters of the procedure
are an 8-bit target output and a TIME period. When called,
it will assign sequential binary numbers from 0 to 255
to its target signal output. These numbers are distanced
by the amount of the constant associated with the period
parameter. You can use the utilities of basic_utilities
package.
5.20) Show the gate level implementation of a master-slave JK
flip-flop. Use the gates on Figure 5.18, and write a
configuration decleration on top of the flip-flop. Use
reasonable delay values and avoid oscillation by using
different delay values for the two cross-coupled gates.
HOMEWORK SET - 4 :
6.2) Write an entity decleration and architecture for an RC
circuit in the qit logic value system. The circuit has an
input and an output. The output follows the input for '0',
'1' or 'X' input values. If the input becomes 'Z', the
output holds its old value for several milli-seconds (use
8 ms).
6.3) Use the RC circuit in Problem 6.2 to describe an NMOS two
input NAND gate. The solution to this problem depends on
code developed in 6.2.
6.6) Using bin2int and int2bin, write a function, inc_qits,
that returns the increment of its qit_vector input
parameter. The output of the function should be qit_vector
type, and values 'X' and 'Z' should be treated as '1'. Use
unconstrained arrays so that your functions works
regardless of the size of the input.
6.10) Write an unconstrained odd parity checker function. The
input is of qit type. Treat values 'X' and 'Z' as '1'.
The function return the XOR results of all its input.
6.12) Speed is distance/time. Write a physical type for speed.
Overload the division operator to evaluate speed when it is
used for dividing distance by time (see Problem 6.4).
[ 6.4) Show type definition for the distance physical
type, ranging from microns to meters. ]
6.15) Write aexpression for detecting the falling edge on a clock
that is the qit type. Falling edge occurs only when the
clock makes a transition from '1' to '0'.
6.18) Repeat Problem 6.7 forunconstrained input a output vectors
. The output of the the shifter should become all 'X' if the
value of c is anything but "00", "01", "10" or "11". Take
advantage of array attributes.
[ 6.7) Use the concatenation operator to develop a
complete VHDL description for an 8-bit logic
shifter. The cicuit has a 2-bit control input
c. The value of c=00 for no-opration, c=01
for right rotate, c=10 is for left rotate, and
c=11 is for arithmetic right shift. The data
input and the output of the circuit are the
qit_vector type, and their mappings determined
by the bits of c. ]
HOMEWORK SET - 5 :
7.6) Write a VHDL description for wiring two decoders in Problem
7.5 to implement 4-t-16 decoder.
[ 7.5) A decoder with an enable input is easily
cascadable. Write a VHDL description for a 3-to-8
decoder with an active low enable input and an
active high enable input. When disabled, all
outputs have to be 0. Use the qit logic value
system. ]
7.11) Write a description for a clocked T-type flip-flop. If T
is '1' on the rising edge of the clock, the outputs of
the flip-flop toggle. Use the qit logic value system.
7.12) Write a VHDL description for a rising edge trigger D-type
flip-flopwith asynchronous set and reset inputs and two
outputs. Label the data, clock, set and reset inputs d,
c, s and r, respectively. Active s or r inputs override
the clocked values on the d input; s and r cannot
simultaneously be active. Changes on d without the rising
edge of c have no effect on the q and qb outputs of the
flip-flop. Use delay parameters sq_delay, rq_delay and
cq_delay for setting, resetting and clocking the
flip-flop respectively. Develop a test bench for testing
this flip-flop. Generate a sample periodic clock using a
conditional signal assignment.
7.13) Given the follwing description, show waveforms on x1, x2
and diff in a timing diagram. Explain the reason for
different wave forms on x1 and x2.
ENTITY find_out IS END find_out;
--
ARCHITECTURE comparing OF find_out IS
SIGNAL c, x1, x2, diff : BIT := '0';
BEGIN
c <= '0' '1' AFTER 60 NS, '0' AFTER 120 NS;
x1 <= '1' AFTER 6 NS WHEN c'EVENT ELSE x1;
x2 <= '1' AFTER 6 NS WHEN NOT c'STABLE ELSE x2;
diff <= x1 XOR x2;
END comparing;
7.15) A resolution function, named all_same, resolves all '1's in
its sources to '1' and all '0's to zero. This function
generates "E", indicating an error condition if conflicting
values are placed at its sources.
A) Declare all necessary types, and write the description
of the all_same function.
B) Declare types and subtypes that can be used for
declaring signals that can take advantage of this
resolution function.
C) Package all of the above and show how a single-bit
signal x and a 16-bit signal x16 should be declared
such that placement of multiple values on these signals
will resolve according to the all_same function.
D) What actual hardware construct behaves like the all_same
function?
7.16) Ten controlled sources ( s(i) where i is 1 to 10) that
range between -25 and +25 volts are connected to the
sources of 10 parallel MOS transistors.The common drain
of these transistors is node n. Each source, s(i), is
controlled by a control line, c(i), that is connected to
the gate of the MOS transistors. Control line voltages
also range between -25 and +25. A control line, c(i),
turns its corresponding transistor on, i.e., causes it
to conduct which in turn causes node n be driven by
source s(i) when c(i) is greater than or equal to +5 volts.
The on-resistance of the parallel transistors is 10 K Ohm.
Node n is also connected to a 25 V supply through a 10 K
Ohm pull-up resistor. At any time, any number of
controlled sources may be active.
A) Write a resolution function that returns the voltage at
node n depending on the value and number of active
sources.
B) In a test architecture, declare a resolved guarded
signal (node n) whose resolution function is that
in Part-A. Use guarded block statements to conditionally
drive the signal (node n) with up to 10 sources, each
of which can take a value between -25 and +25. This is
analogous to connecting 10 parallel MOS transistors to
node n and applying various voltages to the sources of
these transistors. Use a generate statement instead of
10 individiual block statements
7.17) Use a block statement, a resolution function, a conditional
signal assigment and a disconnection specification to model
tri-state noninverting buffer. The gate has data and enable
inputs x and e and output z. When e is '1', the z output is
driven by x; otherwise the output is in the high impedance
state. The inputs and outputs are of type qit and the
output is a guarded signal. Use the three delay values
tp_e_z_float, tp_x_z_high, and tp_x_z_low, where :
tp_e_z_float is for e changing to '0' and causing the
output to disconnect from the input; tp_x_z_low is for e
equal to '1' and x changing to '1' causing the output
become '1', or when x is '1' and e changes to '1'; and
tp_x_z_low is for e equal to '1' and x changing to '0'
causing the output to become '0', or when x is '0' and e
changes to '1'. Use '0' and '1' values for the inputs, and
map 'X' and 'Z' into '0' and '1', respectively. Use two
such buffers for implementing a 2-to-1 multiplexer.
7.21) Write the complete VHDL description for a circuit with an
input x and two outputs, z1 and z2. The circuit consist of
two concurrent Mealy machines. The z1 output becomes '1'
when a 1011 sequence is found on the input, and z2
becomes '1' when a 110 sequence is found on x. Your
description should be capable of having multiple active
states.
7.22) Write a VHDL description for a Moore state machine with
resetting capability. While continuously searching for
1011 on the data input x, if the reset input, r,
becomes '1', the circuit returns to a reset state. In
this state, all previously received data will be ignored,
and a coplete 1011 is required before the output becomes
'1'. While not reset, circuit responds to overlapping
valid sequences.
HOMEWORK SET - 6 :
8.2) Write an assertion statement to issue a warning message if
a negative pulse shorter than 1 us appearson the input
clock.
8.3) Write an assertion statement to issue a warning message if
the frequency of the observing clock is lower than 100 KHz.
If the clock is to slow in some MOS circuits, the circuit
looses information. Assume symetrical clock pulses.
8.4) An equivalent description for the Moore state machine 8.17
is shown here in Fig. 8.41. Modify this description to one
for a Mealy machine detecting the same sequence. Write a
test bench and compare the Mealy and More machine outputs.
Figure 8.41 :
|
ENTITY moore_detector IS
PORT (x, clk : IN BIT; z : OUT BIT);
END moore_detector;
--
ARCHITECTURE behavioral_state_machine OF moore_detector IS
TYPE state IS (reset, got1, got10, got101, got1011);
SIGNAL current : state := reset;
BEGIN
PROCESS
BEGIN
CASE current IS
WHEN reset =>
WAIT UNTIL clk = '1';
IF x = '1' THEN current <= got1;
ELSE current <= reset;
END IF;
WHEN got1 =>
WAIT UNTIL clk = '1';
IF x = '0' THEN current <= got10;
ELSE current <= got1;
END IF;
WHEN got10 =>
WAIT UNTIL clk = '1';
IF x = '1' THEN current <= got101;
ELSE current <= reset;
END IF;
WHEN got101 =>
WAIT UNTIL clk = '1';
IF x = '1' THEN current <= got1011;
ELSE current <= got10;
END IF;
WHEN got1011 =>
z <= '1';
WAIT UNTIL clk = '1';
IF x = '1' THEN current <= got1;
ELSE current <= got10;
END IF;
END CASE;
WAIT FOR 1 NS;
z <= '0';
END PROCESS;
END behavioral_state_machine;
--
|
8.7) Write behavioral description for a dvide-by-n circuit in
which n is passed to it via a generic parameter. The
circuit has an input x and a z output. For every n positive
pulse on x, one positive pulse should appear on z.
8.9) Write a behavioral description for modeling a asynchronous
circuit. The circuit has inputs x and y, and output z. If a
0-to-1 transition on xis immediately followed by a 1-to-0
transition on y (with no other transitions on either input
between these two transitions), the output becomes '1'. The
output stays high until either x changes to '0', or y
changes to '1'. Use process and wait statements.
8.11) Write a procedure (print_hex)to convert an unconstrained
BIT_VECTOR to a string of hexadecimal digits and print it to
a declared file. The subpragram decleration should be
specified this way :
PROCEDURE print_hex (VARIABLE hex : OUT TEXT; bin : BIT_VECTOR);
In this decleration, hex is the open text file object to
which writing to be done, and bin is the binary data to be
printed. Use this procedure in a description as a synchronous
binary up-counter to verify its functioning. Use the method
suggested in Problem 8.10 to implement the counter.
[ 8.10 Write a process to output a 4-bit BIT_VECTOR signal
in hexadecimal. When an event occurs on the signal,
the process become active, and it writes the time
and the hexadecimal representation of the signal to
an output file. To test the process, use it in
description of a synchronous binary up-counter, and
output the counter output to a file named hex_out.
You may use utilities in the basic_utilities
package. The statement shows a simple implementation
of the binary counter:
count <= inc (count) WHEN clk = '1' clk'EVENT ELSE count; ]
8.16) In this problem you will use a 10 value logic system of
integers ranging between 0 and 9. When an input reaches
value 0, it is considered low and when it reaches to 9, it
is considered high.
A) Define ten value type using integer base type.
B) Write a description of an inverter using this value
system. When the input reaches the low level (0), the
output starts switching to high, and linearly changes
from 0 to 9 in 30 ns. When the input reaches the high
level(9), the output starts switching from 9 to 0 in
20 ns. You need not be concerned about the input
changing too fast for the output to respond. Model
linear changes on the output only, considering only
extreme low and high values at the input of the inverter.
8.17) Use the 10 value logic system in the previous problem to
model waveform dependencies in logic gates. Model an
inverter with an input threshold value of 5, so that the
inverter starts switching to its high state when input state
crosses 5 in the downward direction, and starts switching to
its low state when input state crosses 5 in the upward
direction. Complete transitions of the output of the
inverter from high state (9) to low state (0) take 20 ns (2
ns for each state), while the transitions from low to high
takes 30 ns (3 ns for each state). The output should respond
the changes on the input while making a transition, i.e., if
the input switches from 5 to 6 while the output is making a
low-to-high transition, the direction of of the the output
should change. This is not an easy problem. Also, you can
easily modify this problem to make the speed of the output
depend on the speed of the input.
HOMEWORK SET - 7 :
9.2) In Parwan assembly code, write a program to move a block of
data that is stored in the memory. The data begins at
location 4:00 and ends at 4:63, and is to bo moved to page 5
starting at 5:64.
9.4) Show the VHDL description of the Mark-1 machine whose ISPS
description appeared in Figure 1.3 of Chapter 1.
Figure 1.3 : An ISPS example, a simple processor.
(Source: M. R. Barbacci, The ISPS Computer
Description Language, Carnegie-Mellon
University, 1981, p. 70)
|
mark1 :=
BEGIN
** memory.state **
m[8:8191]<31:0>
** processor.state **
pi\present.instruction<15:0>'
f\function<0:2> := pi<15:13>,
s<0:12> := pi<12:0>,
cr\control.register<12:0>
acc\accumulator<31:0>,
** instruction.execution ** {tc}
MAIN i.cycle :=
BEGIN
pi = m[cr]<15:0> NEXT
DECODE f =>
BEGIN
0\jmp := cr = m[s],
1\jrp := cr = cr + m[s],
2\ldn := acc = - m[s]
3\sto := m[s] = acc,
4:5\sub := acc = acc - m[s],
6\cmp := IF acc LSS 0 => cr = cr+1,
7\stp := STOP(),
END NEXT
cr = cr+ 1 NEXT
RESTART i.cycle
END
|
HOMEWORK SET - 8 :
9.10) Parwan can be modified to use only three bits for
distinguishing between various non-address instructions. We
can, therefore, reserve bit 3 of the instruction register as
an opcode bit for extending Parwan instructions.In addition,
two more non-address instructions can be added to the Parwan
instructions. Modfy the behavioral descrioption of Parwan
such that non-address instructions use 11100xxx opcode. For
xxx use 000, 001, 010, 100, and 101 for nop, cla, cma, cmc,
asl and asr, respectively.
9.12) Add a stack pointer to the register and bussing structure of
Parwan for the implementation of a software stack. Restrict
the stack to the last page of the memory. Use the method of
opcode expansion suggested in Problem 9.10 to make room for
a new instruction, and use 11101001 for an lds instruction
that loads the stack pointer with the data in the next
instruction byte. Show all bus connections, registers and
necessary control signals.
9.13) Use the method suggested in Problem 9.10, and stack pointer
of Problem 9.12 to add two new non-address instructions,
push and pop. Use 11100110 for push, and 11100111 for pop.
Modify the behavioral description of Parwan for the
execution of these instructions.
HOMEWORK SET - 9 :
9.16) Show the dataflow implementation of the opcode extension
scheme suggested in Problem 9.10. Show all required bus
connections, and modify the controller of Parwan.
9.18) Modify the Parwandataflow description for the implementation
of lds, push and pop instructions (see Problems 9.12 & 9.13).
Show all required bus connections, write a description for
the stack pointer (sp), and insert this unit in the datapath
description of Parwan. Also, modify the Parwan controller to
properly execute this instruction.